I am planning to simulate and implement a buck converter in an bread board.So I was searching all over the web for good material to understand and design it.I could find that none of the texts followed at universities is not good enough for implementation of the circuit physically(I really dont understand the reason the universities provide us with such texts to follow and judge every one based on the marks they get by following such texts --- Ever have you wondered why the students with low marks who tries perform so badly... Just think of this context.)

Anyway I was able to find many such papers from internet explaining the basics of it and I found this particular one very easy to understand and follow.I must really thank Bob Dildine who is its author to prove its not rocket science but its all about the concept and less about the equations thats proves it.

Notes I made while designing the buck converter using the above mentioned(Link to download the Buck Converter basics Notes is given at the end of this post).

How it works:TICK

The Math choosing the inductor : ALL ARE TICK EXCEPT WHEN SAID NOT SO.

1. Inductor current made of the Load current(Since in series with load) and the Ripple current.

2. PP Ripple is set as 30 - 40 % of the load current at start of the design(Later this value could be bought down to our requirements while tweaking for a beginner).

3. I ripple = (1/L*(V*T)), where V is the voltage across the inductor and the T is the time for which  the current flow through the inductor in a cycle.

4. I ripple through the switces S1 and S2 are the same. -- NOT TICK

5. From the equation for I ripple we can choose the i )Value of the inductor.
                                                                                 ii )Switching Frequency.

For a given current and voltage difference around the inductor the inductor value is proportional to the switching frequencey.ie; Inductor value DECREASES as Switching Frequency of the switch in series with inductor INCREASES.

BUT with losses in the inductor and switches increases with frequency PRATICAL LIMIT as of now is around 1MHz(as said by Bob Dildine).

My Design parameters and requirements (Trying the values as said in the paper)

Source Voltage : 12V

Load Voltage    : 6 V

Load current     : 0.6 A (I have doubt may change it)

Switching Frequency : I am here trying for two frequencies i)400Khz ii) 50Khz

Because my  MOSFET'S  (Texas Instrument's - CSD13303W1015 (ACTIVE)N-Channel NexFET™ Power MOSFET) has very low rise time and fall time of 10ns and 3.2ns.

It has very low on state resistance(This and Rise and fall time is what I have checked now for selecting the mosfet).

My  LAB  Sir (I am not putting his name here without his permission but I Must he is definetley one of the Most Influential Teachers I ever had in my life ) said that switching at higher than 100Khz requires expertise of seasoned power electronics engineer but I don't want to leave what frequency I had in my mind for doing the circuit.I am therefore calculating for both the values.

Ripple Current : Assuming 30 % of the load current in addition to load current passing through the inductor(My inference) = 0.3 * 0.6 = 1.8 A

Inductor : Found using the Equation for I ripple

S1's duty cycle = (Load voltage)/(Source Voltage) = 0.5
Period of switching cycle = case(i)For  400 Khz = (1/400000) = 2. 5 microseconds
                                             case(ii)For   50 Khz = (1/50000)   = 20   microseconds
Time for which the Switch S1 is ON Delta t S1
 = 0.5 * 2.5 ms  = 1.25 microsecs case(i)
 = 0.5 * 20 ms  =  10microsecs     case(ii)

L Inductor Value
= ((12-6)*1.25)/0.18)=41.67microhenry case (i)
= ((12-6)*10)/0.18)   =333.34 microhenry case(ii)

Notice a couple of things about the inductor value. It’s proportional to the time that S1is on which implies that it’s inversely proportional to the switching frequency. And it’s inversely proportional to the ripple current which implies that it’s inversely proportional to the load current. So as the switching frequency increases, you need less inductance and as the load current increases you need
less inductance. But this also means that for a certain value of inductor there is minimum practical load current. It’s sort of analogous to the critical inductance in a choke input filter for a traditional linear power supply.

Might have to go through the Jim williams Application note if I have to choose an inductor(I may have to Because If didn't get the specific MOSFET I was searching for from TI).

The Output Capacitor and ESR Value : TYPICAL Req C and Low ESR

This Capacitor makes the ripple effect of the Inductor to be less scene on the Load Side.

For this Capacitor must be able to store and discharge the rippled current.

Wat it means is capacitorcharges to the alternating nature of the rippled current from the
the inductor and discharges it into the ground.

so its impedance (its reactance Xcplus its equivalent series resistance, ESR and its equivalent series
inductance, ESL) must be low enough that the ripple current times the impedance is less than
the desired output voltage ripple ---- NOT TICK

Better Explanation from the LC Design guide from ONSEMIconductors.

The output capacitance directly affects the output voltageof the converter, the response time of the output feedbackloop, and the amount of output voltage overshoot that occurs uring changes in load current. A ripple voltage exists on theDC output as the current through the inductor and capacitor
increases and decreases.
Increasing the capacitance reduces he amount of ripple voltage present. However, there is tradeoff between capacitance and the output response.Increasing the capacitance reduces the output voltage ripple nd output voltage overshoot, but increases the time it takesthe output voltage feedback loop to respond to changes inload.
Therefore, a minimum capacitance must be considered,in order to meet the ripple voltage and voltage overshootrequirements of the converter, while maintaining a feedbackloop that can respond quickly enough to load changes.
Capacitors also have a parasitic series resistance, knownas the equivalent series resistance (ESR). The ESR impactsthe output voltage ripple and the overall efficiency of theconverter. Because of this, designers are moving to low ESRdesigns. Surface mount ceramic capacitors are becomingprevalent in systems that require high performance in asmall form factor. The use of multiple capacitors in parallelallows designers to achieve the necessary capacitance forthe system while greatly reducing the equivalent ESR. 

Buck Converter Demystified by Donald Schelle and Jorge Castorena

** I Might in the future redesign the Inductor according to this paper cause this one seems a good bet
     at producing the correct output even though the Calculations involved are more tiresome.

As of my understanding until now,

 The Capacitor Selection requires us to set a goal regarding what is the Maximum overshoot that may appear in the load voltage.This Overshoot in the voltage is the result of the dumping of inductor to the series connected load when the load is taken of momentarily or permenently.So the capacitor must be able to keep a watch on the maximum overshoot of voltage at the output.

Also there is large voltage ripple caused by this capacitor which shows up in the load.This Voltage ripple is not majorily because of the capacitance if the capacitance is so choosen to just charge and
discharge the ripple voltagedue to inductor + ( I think the capacitance must also take care of the
ESL in the capacitance resulting in the formation of the ripple in the current supplied to load adding the ripple in the voltage )But it is the ESR part of the Capacitor that acts as MAJOR SHARE of cont
-ribution towards the Voltage ripple in the load.

So We Must choose the Capacitance Value more than/equal to than required by the overshoot prevention.While the ESR value must be choose must be lower than what is allowed without
affecting the voltage ripple to the worse.

Capacitance value at the output :

** These things may change with the material of the capacitor.This will be dealt with later(From Bob Dildine's Article).

CASE (i) Allowed Overshoot of 100mv @ 41.67microH

C = 23.733microF but with 20% tolerance = 28.4664microF(If going for Capacitor at rated voltage  else choose the original value of capacitance and choose a capacitor at 3 times more rated value)

CASE (ii)Allowed Overshoot of 100mv @ 333.34microH

C = 190.086microF but with 20% tolerance = 228.103microF

ESR value at the output (Maximum Allowed ): EQN from demystifed  guide,

Vout ESR = I ripple * ESR capacitorop

CASE(i) ESR = 555.5milliohm
CASE(ii)ESR = 533.6milliohm

Allowed ESR Must be less than these values.

Input Capacitor Selection: From Bob Didline cause it made more sense to me.

 The dc component of the input current is the average of this rectangular pulse and is simply S1’s duty cycle times the load current

The capacitor supplies the input current’s ac component.

Irms ip = Iout load* D*Sqareroot of (1-D )

Input Capacitor is thus choosen according to this value of RMS component of current that has to be
provided by the source to the Inductor.And I think ESR is secondary priority cause once we find capacitor that may be able to withstand the current ripple neccesary to give  across the inductor with the same avg i/p current left over part of the ripple current at the input is periodically taken through
the capacitor(As by current divion rule---This is my guess kindly do correct me If I am wrong ).

Irms = 0.212A

Strange as it may seem, the input capacitor is chosen based on its ESR and current rating rather
than its capacitance value.

SWITCH SELECTION : Now done randomnly,** Will deal with proper selection later.

I am planning to do the Two MOSFET based synchronous converter for the Buck circuit.So I have avoided the schottky diode.The MOSFET currently I am planning to use is already mentioned as is

Texas Instrument's - CSD13303W1015 (ACTIVE)N-Channel NexFET™ Power MOSFET.

- Bread Board
-Two Mosfets
-Connecting wires

Following mentioned point was taken under consideration while choosing this MOSFET,

The power lost through the series FET,Q1 is due not only to its dc on resistance, but also to transition losses caused by pumping current into and out of its Miller capacitance --- TICK
So while it’s best to select a low resistance FET for Q2, you need to balance the FET’s Miller capacitance against its on resistance for Q1-- NOT TICKED

Have to go through the application notes for more getting into this matter!!


Purchases has to done.
Simulation of the simple buck converter with above value has tobe done.
Practical Circuit with the proper driver circuit must be designed.
Simulation with practical circuit.
Hardware Implementation.
Updating the Blog with details as when it is done.

The Ideas mentioned above has been done solely for my purposes I do not advice anyone to do the same nor shall I take the responsibility of any harm that happen to you by the above mentioned data usage in your work.If any errors please do point it out.


Links to materials followed  : Equations used are from this papers

Bob Didline Material

Buck converter Demystified


Leave a Reply